Semiconductor storage device, redundancy circuit thereof, and portable electronic device

ABSTRACT

A semiconductor storage device includes a plurality of memory elements and a redundancy circuit. Each of the memory elements includes (i) a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, (ii) a channel region provided under the gate electrode, (iii) diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and (iv) memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge. The redundancy circuit includes an addressing arrangement for a single chip memory including cells associated with a plurality of redundant lines. A decoder for selecting a redundant row is selected by an address signal, and the decoder is programmed. The redundancy circuit requires no additional package pin, and programming is executed after packaging is completed. The semiconductor storage device further includes an arrangement for permanently inactivating any further programming of the redundancy circuit, in order to prevent a user from performing inadvertent programming.

This Nonprovisional application claims priority under 35 U.S.C. § 119(a) on Patent Application No. 2003/142644 filed in Japan on May 20, 2003, the entire contents of which are hereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates, in particular, to a redundancy circuit used in a semiconductor storage device, such as a single-chip memory.

BACKGROUND OF THE INVENTION

Conventionally, a flash memory has been used as a nonvolatile memory.

In this flash memory, as shown in FIG. 28, a memory cell is constituted such that a semiconductor substrate 901 includes thereon, via a gate insulating film, a floating gate 902, an insulating film 907, and a word line (control gate) 903 in this order, and a source line 904 and a bit line 905 are formed on both sides of the floating gate 902. Around the memory cell, an element separation region 906 is formed (for example, Japanese Laid-Open Patent Application No. 304277/1993 (Tokukaihei 5-304277; published on Nov. 16, 1993).

The memory cell holds memory depending upon the amount of charges in the floating gate 902. A memory cell array which is an array of memory cells enables rewriting and read-out operations with respect to intended memory cells by applying a predetermined voltage to particularly selected word lines and bit lines.

Such a flash memory shows drain current (Id) to gate voltage (Vg) characteristics as shown in FIG. 29 with variation in the amount of charges in the floating gate. Increase in the amount of negative charges in the floating gate increases a threshold value, and an Id-Vg curve moves substantially parallel to the direction where Vg increases.

However, such a flash memory has the following problems: it is functionally necessary that the insulating film 907 is placed to isolate the floating gate 902 from the word line 903; and it is difficult to reduce the thickness of the gate insulating film to prevent leakage of charges from the floating gate 902. Therefore, it is difficult to realize the reduction in thickness of the insulating film 907 and the gate insulating film, interfering with the realization of a finer memory cell.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor storage device and a portable electronic device which are easy to miniaturize.

To attain the foregoing object, the redundancy circuit of the present invention is useful for a memory in which first address signals are used to select first lines (e.g. row lines) in the array, and second address signals are used to select second lines (e.g. bit lines). The redundancy circuit of the present invention includes a plurality of redundant row lines. Programmable decoder means is provided for selecting row lines when a predetermined row address signals are inputted to the memory. These row address signals correspond to addresses of defective row lines. The redundancy circuit includes selecting means which receives address signals of the second lines (bit lines). The selecting means selects the programmable decode means during programming, thereby preventing further programming. Once a redundant line replaces a defective line in the memory array, further unnecessary programming will be prevented permanently. Once a redundancy line is selected, all unassociated lines are deselected.

A memory element which is included in the memory is a switching memory, that is, a memory element including (i) a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, (ii) a channel region provided under the gate electrode, (iii) diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and (iv) memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge.

The redundancy circuit of the present invention can be used for the redundant rows as described above, or may be used for redundant columns by selecting the programmable decoder means with row addresses.

The memory is programmed to use the redundant lines, and then programmed to prevent inadvertent programming. In addition, the memory is programmed to replace defective lines with redundant lines, thereby preventing inadvertent programming.

For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional diagram schematically showing a main part of a memory element in a semiconductor storage device of Embodiment 1 of the present invention.

FIGS. 2(a) and 2(b) are cross-sectional diagrams each schematically showing a main part of a modified memory element in the semiconductor storage device of Embodiment 1 of the present invention.

FIG. 3 is a diagram explaining writing operation of the memory element in the semiconductor storage device of Embodiment 1 of the present invention.

FIG. 4 is a diagram explaining another writing operation of the memory element in the semiconductor storage device of Embodiment 1 of the present invention.

FIG. 5 is a diagram explaining erasing operation of the memory element in the semiconductor storage device of Embodiment 1 of the present invention.

FIG. 6 is a diagram explaining another erasing operation of the memory element in the semiconductor storage device of Embodiment 1 of the present invention.

FIG. 7 is a diagram explaining read-out operation of the memory element in the semiconductor storage device of Embodiment 1 of the present invention.

FIG. 8 is a cross-sectional diagram schematically showing a main part of a memory element in a semiconductor storage device of Embodiment 2 of the present invention.

FIG. 9 is a magnified cross-sectional diagram of a main part of a modified memory element in FIG. 8.

FIG. 10 is a magnified cross-sectional diagram of a main part of a modified memory element in FIG. 8.

FIG. 11 is a graph showing an electric property of a memory element in a semiconductor storage device of Embodiment 2 of the present invention.

FIG. 12 is a cross-sectional diagram schematically showing a main part of a modified memory element in the semiconductor storage device of Embodiment 2 of the present invention.

FIG. 13 is a cross-sectional diagram schematically showing a main part of a memory element in the semiconductor storage device of Embodiment 3 of the present invention.

FIG. 14 is a cross-sectional diagram schematically showing a main part of a memory element in the semiconductor storage device of Embodiment 4 of the present invention.

FIG. 15 is a cross-sectional diagram schematically showing a main part of a memory element in the semiconductor storage device of Embodiment 5 of the present invention.

FIG. 16 is a cross-sectional diagram schematically showing a main part of a memory element in the semiconductor storage device of Embodiment 6 of the present invention.

FIG. 17 is a cross-sectional diagram schematically showing a main part of a memory element in the semiconductor storage device of Embodiment 7 of the present invention.

FIG. 18 is a cross-sectional diagram schematically showing a main part of a memory element in the semiconductor storage device of Embodiment 8 of the present invention.

FIG. 19 is a graph showing an electric property of a memory element in a semiconductor storage device of Embodiment 9 of the present invention.

FIG. 20 is a circuit diagram illustrating a main part of a redundancy circuit (Embodiment 10) used in a semiconductor storage device including a memory element of Embodiments 1 through 8.

FIG. 21 is a circuit diagram illustrating a circuit for generating signals to be supplied to buffers in the redundancy circuit.

FIG. 22 is a circuit diagram illustrating a programmable buffer provided in the redundancy circuit.

FIG. 23 is a circuit diagram illustrating another programmable buffer provided in the redundancy circuit.

FIG. 24 is a circuit diagram illustrating a fuse-blowing circuit provided in the redundancy circuit.

FIG. 25 is a circuit diagram illustrating another programmable circuit using the memory element of the present invention.

FIG. 26 is a schematic diagram of a liquid crystal display device (Embodiment 11) including a semiconductor storage device of Embodiment 10 of the present invention.

FIG. 27 is a schematic diagram of a portable electronic apparatus (Embodiment 12) including a semiconductor storage device of Embodiment 10 of the present invention.

FIG. 28 is a cross-sectional diagram schematically showing a main part of a conventional flash memory.

FIG. 29 is a graph showing an electronic property of a conventional flash memory.

DESCRIPTION OF THE EMBODIMENTS

The following describes embodiments of the present invention with reference to FIG. 1 through FIG. 27.

A semiconductor storage device of the present invention mainly consists of a memory element and a control circuit for storing data in the memory element.

The memory element mainly consists of a semiconductor layer, a gate insulating film, a gate electrode, a channel region, a diffusion region, and a memory functioning member. Here, the channel region, whose conductivity type is identical to a conductivity type of the semiconductor layer, means a region beneath the gate electrode. The diffusion region means a region whose conductivity type is opposite a conductivity type of the channel region.

Specifically, the memory element (device) of the present invention may be provided with a first conductive region (which acts as a diffusion region), a second conductive region (which acts as a channel region), a memory functioning member, a gate insulating film, and an electrode. The first conductive region is of a first conductivity type (either n- or p-type), and the second conductive region is of a second conductivity type, that is, of the other type (where the first conductive region is n-type, the second conductive region is p-type, and vice versa). The memory functioning member is provided over a boundary between the first and second conductive regions. The gate insulating film is provided between the memory functioning member and the electrode. However, it is appropriate that the memory element is so arranged as to include (i) a gate electrode provided on a gate insulating film, (ii) two memory functioning members provided on both sides of the gate electrode, (iii) and two diffusion regions provided such that the memory functioning members are respectively sandwiched between each diffusion region and the gate electrode, and (iv) a channel region provided under the gate electrode.

A semiconductor device of the present embodiment is preferably arranged such that the device is formed on a well region of the first conductivity type, the well region being formed on a semiconductor substrate or preferably in the semiconductor substrate, and acting as a semiconductor layer. The semiconductor substrate is not particularly limited, provided that the semiconductor substrate is applicable for a semiconductor device. For example, a bulk substrate made from an element semiconductor or a compound semiconductor may be used. Examples of the element semiconductor are silicon, germanium, and the like. Examples of the compound semiconductor are silicon germanium, GaAs, InGaAs, ZnSe, GaN, and the like. Moreover, the semiconductor substrate may be a substrate whose top layer is a semiconductor layer. Examples of this type of the substrate are: various substrates such as SOI (Silicon on Insulator) substrates, SOS substrate, multi-layer SOI substrate; and a substrate having a semiconductor layer on a substrate made of glass or plastic. Of those substrates, the silicon substrate, the SOI substrate (whose top layer is a silicon layer) and the like are preferable. The semiconductor substrate and the semiconductor layer may be monocrystal (for example, produced by epitaxial growth), polycrystal, or amorphous, even though an amount of current flowing therethrough varies depending on whether they are monocrystal, polycrystal, or amorphous.

It is preferable that an element separating region is provided on the semiconductor layer. By further including, in combination, an element (such as a transistor, a capacitor, and/or a resistor), a circuit formed by using the elements, a semiconductor device, and/or an interlayer-insulating. film, the semiconductor layer may have a single-layer structure or a multi-layer structure. Note that the element separating region may be formed from an element separating film such as an LOCOS film, a trench oxide film, an SI film, and the like. The semiconductor layer may be either p-type conductive or n-type conductive. It is preferable that the semiconductor layer is provided with at least one well region of the first conductivity type (p-type or n-type). As the semiconductor layer and the well region, it is possible to use a semiconductor layer and the well region whose impurity concentration is within a range generally used in a field in which the semiconductor device is to be used. In case where the SOI substrate is used to provide the semiconductor layer, the semiconductor layer, which is a top layer and may be provided with a well region, may be provided with a body region under a channel region.

The gate insulating film is not particularly limited, provided that the gate insulating film is a gate insulating film generally used in a semiconductor device. For example, the gate insulating film may be an insulating film such as a silicon oxide film, a silicon nitride film, or the like; a single-layered high dielectric film or a laminate film including the high dielectric film (the high dielectric film may be an aluminum oxide film, titanium oxide film, a tantalum oxide film, a hafnium oxide film, or the like).

Of those films, the silicon oxide film is preferable. The gate insulating film may have a thickness of, for example, about 1 nm to 20 nm, preferably of 1 nm to 6 nm. The gate insulating film may be provided only right under the gate electrode, or may have a size larger (a width wider) than the gate electrode.

The gate electrode is provided on the gate insulating film, and has a shape that is usually used in a semiconductor device, or a shape having a recess section in its bottom end portion. It is preferable that the gate electrode has an integrated shape without being separated by using a single-layered or a multi-layered conductive film. However, the gate electrode may be so arranged as to have a shape that is separated by using a single-layered or a multi-layered conductive film. Moreover, the gate electrode may be provided with a side-wall insulating film on its side. The gate electrode is not particularly limited, provided that the gate electrode is a gate electrode generally used in a semiconductor device. The gate electrode may be formed from a conductive film, which may be a single-layered or laminate film prepared from: polysilicon; a metal such as copper, aluminum, or the like; a metal having a high melting point, such as tungsten, titan, tantalum or the like; a silicide of the metal having the melting point; or the like. It is appropriate that the gate electrode has a thickness in a range of from 50 nm to 400 nm approximately, for example. Note that the channel region is formed under the gate electrode.

It is preferable that the gate electrode is provided only on a side wall of a memory functioning member later described, or is so provided as not to cover a top part of the memory functioning member. Those arrangements allow to provide a contact plug in a vicinity of the gate electrode. Therefore, this arrangement makes it easier to attain finer memory element. Moreover, the memory element having the simple arrangement as described above can be easily produced, thereby attaining a better yield.

The memory functioning member at least has a function to hold electric charges (hereinafter, this function is referred to as charge-holding function). In other words, the memory functioning member is configured (i) to accumulate and hold electric charges (charges), (ii) to trap electric charges, or (iii) to stay under an electric charge-polarized condition. The charge-holding function is attained in the memory functioning member, by providing the memory functioning member with a film or a region, which has a function to hold electric charges. Examples of materials to give the charge-holding function are: silicon nitride; silicon; silicate glass containing impurity such as phosphorus, boron, and/or the like; silicon carbide; alumina; high dielectric materials such as hafnium oxide, zirconium oxide, tantalum oxide, and the like; zinc oxide; ferroelectric substances; metals; and the like. Therefore, the memory functioning member may have a single-layered or laminated structure formed from, for example, (i) an insulating film including the silicon nitride film, (ii) an insulating film including a conductive layer or a semiconductor layer; an insulating layer including at least one dot made of a conductive material or a semiconductor material; an insulating film including a ferroelectric film in which polarization of electric charge is caused by applying an electric field and then is maintained; and the like film. Of those films, the silicon nitride film is preferable. The reasons why the silicon nitride film is preferable are as follows: a large hysteresis property can be attained because the silicon nitride film has a large number of levels for trapping electric charges; a good holding property can be attained by the silicon nitride film because the silicon nitride film holds the electric charge for a long time thereby preventing leak path, which causes electric charge leakage; and the silicon nitride film is a raw material used as standard in the LSI process.

With the arrangement in which the memory functioning member is provided with the film (such as the silicon nitride film or the like) having the charge-holding function, it is possible to attain more reliable memory holding function. Because the silicon nitride film is an insulator, electric charge leakage in part of the silicon nitride film will not lead to immediate loss of electric charge from the whole silicon nitride film. Moreover, in case where a plurality of memory elements (devices) are arrayed, this arrangement prevents erasure of data stored in a memory functioning member that touches an adjacent memory functioning member when the memory elements (devices) get closer to each other, on contrary to an arrangement in which the memory functioning members are conductive. Further, this arrangement allows to provide the contact plug in a greater vicinity of the memory functioning member. In some cases, this arrangement allows the contract plug to be so provided as to overlap the memory functioning member. Thus, this arrangement makes it easier to attain a finer memory element.

Note that the film having the charge-holding function is not necessarily in a film-like shape. Even if the film having the charge-holding function is not in the film-like shape, the more reliable memory holding can be attained. It is preferable that pieces of the film having the charge-holding function are dispersed (scattered) inside the insulating film. Specifically, it is preferable that the pieces of the film having the charge-holding function are scattered in a material in which electric charges are hardly held, for example, in silicon oxide, in such a manner that the pieces are scattered in the material as if dots scattered in the material.

In case where a conductive film or a semiconductor layer is used as the film having the charge-holding function (charge holding film), it is preferable that the charge holding film is so provided that (i) the charge holding film and (ii) the semiconductor layer (semiconductor substrate, well region, body region, source region, drain region, or diffusion region) or the gate electrode are separated by the insulating film provided therebetween, so that the charge holding film will not directly touch the semiconductor layer or the gate electrode. For example, this arrangement can be attained by (i) a laminate structure in which the conductive film is provided on the insulating film, (ii) a structure in which pieces of the conductive film are scatted, as if dots scattered therein, in the insulating film, (iii) a structure in which a conductive film is provided in part of side-wall insulating film formed on a side wall of a gate, or (iv) the like structure.

The arrangement is preferable in which the insulating film including the conductive film or the semiconductor film is used as the memory functioning member, because this arrangement makes it possible to freely control an amount of electric charges entering a conductor or a semiconductor in the memory functioning member, thereby making it easier to attain multi-valued property. Furthermore, the arrangement is preferable in which the insulating film including at least one dot made of a conductive material or a semiconductor material is used as the memory functioning member, because this arrangement makes it easier to write and erase by direct tunneling of charges, thereby attaining lower power consumption.

Moreover, the memory functioning member may be a ferroelectric film whose polarization direction is changeable according to electric field. The ferroelectric film may be PZT (Lead Zirco-Titanate) family ferroelectric film, PLZT (Lead Zirco-Titanate) family ferroelectric film, or the like film. In this arrangement, polarization causes generation of charges substantially on a surface of the ferroelectric film. The charges thus generated are held. Therefore, it is possible to attain the hysteresis property that is similar to the hysteresis property attained by a film having a function to trap charges supplied from an outside of a film having a memory function. Furthermore, in order to hold the charges therein, the ferroelectric film needs no external supply of the charges in this arrangement. The ferroelectric film can attain the hysteresis property simply by polarization of the charges inside the film. Thus, fast writing (programming) and erasing can be realized by this arrangement. Therefore, this arrangement is preferable.

Note that it is appropriate to arrange such that the insulating film included in the memory functioning member is a region from which the charges hardly leak out, or a film having a function of making it difficult for the charges to leak out. For example, a silicon oxide film or the like has the function of making it difficult for the charges to leak out.

The charge holding film to be included in the memory functioning member is provided directly on each side of the gate electrode. Alternatively, the charge holding film is provided indirectly on each side of the gate electrode with the insulating film sandwiched between the charge holding film and the gate electrode. Further, the charge holding film is provided on the gate insulating film (semiconductor substrate, well region, body region, source region, drain region or diffusion region) indirectly or directly, that is, with or without a gate insulating film sandwiched therebetween. It is preferable that the side walls of the gate electrode are partially or wholly covered with (i) the charge holding films provided directly thereon or (ii) the charge holding films provided indirectly thereon with the insulating film sandwiched between the charge holding film and the side wall of the gate electrode. As a specific example of usage, if the gate electrode has a recess section in its bottom end portion, the charge holding film may be formed such that the recess section is partially or completely filled with (i) the charge holding film provided directly on the gate electrode or (ii) the charge holding film provided indirectly on the gate electrode with the insulating film sandwiched between the charge holding film and the gate electrode.

The diffusion region may function as the source region and drain region, and has a conductivity opposite a conductivity of the semiconductor layer or the well region. It is preferable that impurity concentration changes steeply over the junction between the diffusion region and the conductive layer or the well region. This arrangement makes it possible to attain efficient generation of hot electrons or hot holes by using a low voltage, thereby attaining a high-speed operation by using a lower electrode. The diffusion region is not particularly limited in terms of depth of its junction. Thus, the depth of the junction of the diffusion region may be arbitrarily adjusted depending on properties and the like of the semiconductor storage device to be obtained. In case where the semiconductor substrate is an SOI substrate, the depth of the junction of the diffusion region may be shallower than a thickness of the top-layer semiconductor layer. However, it is preferable that the depth of the junction is approximately equivalent to the thickness of the top-layer semiconductor layer.

The diffusion regions may be so provided as to (i) overlap with an end of a gate electrode, (ii) be located on the end of the gate electrode but not beyond the end of the gate electrode, or (iii) be offset with respect to the gate electrode terminal. Especially in case where the diffusion region is offset with respect to the gate electrode terminal, an offset region under the charge holding film is reversed when a voltage is applied on the gate electrode. An amount of the charges accumulated in the memory functioning member largely changes how easily the offset region is reversed. Thus, in case where the diffusion region is offset with respect to the gate electrode terminal, a higher memory effect and reduction in short-channel effect are attained. Therefore, it is preferable that the diffusion region is offset with respect to the gate electrode terminal. However, if the diffusion region is offset too much, a driving current across the diffusion region (between source and drain) becomes small significantly. Therefore, it is preferable that an offset amount (a distance in a gate length direction between one gate electrode terminal and the diffusion region that is closer to the gate electrode terminal) is shorter than a thickness of the charge holding film, the thickness being parallel to the gate length direction. It is especially important that at least part of the charge holding film (a film having the charge holding function) in the memory functioning member overlaps part of the diffusion region. This is important because the memory element constituting the semiconductor storage device performs its data rewriting operation by using an electric field across the memory functioning member, the electric field generated by an voltage difference between the gate electrode and the diffusion region, the voltage difference existing only on the side wall of the memory functioning member.

The diffusion region may be so arranged that part of the diffusion region is located on a surface of the channel region, that is, in a position higher than a lower surface of the gate insulating film. In this arrangement, it is appropriate that a conductive film integrated with the diffusion region is provided on the diffusion region formed in the semiconductor substrate. The conductive film is, for example, made of (i) a semiconductor such as polysilicon, amorphous silicon, or the like, (ii) a silicide, (iii) any one of the above-mentioned metals and the metals having a high melting point, or (iv) the like. Of those materials, polysilicon is most preferable. Polysilicon has an impurity diffusion rate much greater than that of the semiconductor layer. Because of this, the use of polysilicon makes it easier to attain the diffusion region whose junction has a shallower depth in the semiconductor layer. This makes it easier to suppress the short channel effect. Note that, in this arrangement, at least part of the memory functioning member is sandwiched between the gate electrode and the part of the diffusion region.

The memory element of the present embodiment may be formed via a semiconductor process generally used, for example by a method similar to a method of forming a single-layered or laminated structured side wall spacer on the side wall of the gate electrode. Specifically, the memory element may be formed by the following methods: (1) after forming the gate electrode, formed is a single-layered film or a laminate film including the film (hereinafter “charge holding film”) having the function of holding the charge (the single-layered film or a laminate film may be a single layer of the charge holding film, a laminate film structured as the charge holding film/the insulating film, a laminate film structured as the insulating film/charge holding film, a laminate film structured as the insulating film/charge holding film/insulating film, and the like film). And then, the film is etched backed under an appropriate condition so that the film retains a side-wall-spacer-like shape; (2) one of the insulating film and the charge holding film is formed and then etched back under an appropriate condition so that the film retains the shape of the side wall spacer. Thereafter, the other one of the insulating film and the charge holding film is formed and then etched back similarly so that the film retains the side-wall-spacer-like shape; (3) An insulating film material in which particles of a charge holding material are dispersed is applied or deposited on the semiconductor layer including the gate electrode, thereby forming a film of the insulating material. The film is etched back under an appropriate condition so that the insulating film material retains the side-wall-spacer-like shape; (4) after forming the gate electrode, the single-layered film or the laminated film mentioned above is formed, and then subjected to patterning by using a mask; and (5) the like methods. Moreover, the memory element may be formed by the following method or the like method: before forming the gate electrode, formed is the charge holding film, the laminate film structured as charge holding film/insulating film, the laminate film structured as insulating film/charge holding film/insulating film, or the like film. And then, an aperture is formed in a region that is to be the channel region of the film. After that, the film of the gate electrode material is formed all over the aperture. Subsequently, the film of the gate electrode material is patterned in a shape that includes the aperture and is larger than the aperture.

How to form the memory element in this method is explained below, referring to a memory element shown in FIG. 8. To begin with a gate insulating film 214 and a gate electrode 217 are formed on a semiconductor substrate 211 via a well-known process. Next, on a whole surface of the semiconductor substrate 211, a silicon oxide film 241 is formed by the thermal oxidation method or deposited by the CVD (Chemical Vapor Deposition) method. The silicon oxide film 241 has a thickness of 0.8 nm to 20 nm, preferably of 3 nm to 10 nm. Then, on a whole surface of the silicon oxide film 241, a silicon nitride film 242 is deposited by the CVD method, the silicon nitride film 242 having a thickness of 2 nm to 15 nm, preferably of 3 nm to 10 nm. Further, on a whole surface of the silicon nitride film, a silicon oxide film 243 having a thickness in a range of 20 nm to 70 nm is formed by the CVD method. In this way, a laminate of silicon oxide film/silicon nitride film/silicon oxide film is formed.

Next, the laminate of silicon oxide film/silicon nitride film/silicon oxide film is etched back by anisotropic etching. Thereby, memory functioning members 261 and 262 having the side-wall-spacer-like shape are formed on the gate electrode 217. The thus formed memory functioning members 261 and 262 are suitable for recording operation.

After that, diffusion regions (source/drain regions) 212 and 213 are formed by ion introduction during which the gate electrode 217 and the memory functioning members 261 and 262 having the side-wall-spacer-like shape are used as masks. After the formation of the diffusion regions 212 and 213, the silicide process and the process of forming upper wiring are performed via the well-known process.

In case where a memory cell array is formed by arraying the memory elements (devices) of the present embodiment, a best arrangement of the memory element (devices) satisfy all of the followings requirements, for example: (1) gate electrodes of a plurality of memory elements (devices) are connected together and function as a word line; (2) memory functioning members are provided respectively on both sides of the word line; (3) an insulator, especially a silicon nitride film has a function of holding charges in each memory functioning member; (4) the memory functioning members are formed from ONO (Oxide Nitride Oxide) films, and the silicon nitride film has a surface that is substantially parallel to a surface of the gate insulating film; (5) the silicon nitride film inside the memory functioning member is separated from the word line and a channel region by a silicon oxide film; (6) the silicon nitride film inside the memory functioning member overlaps a diffusion region; (7) the insulating film and the gate insulating film are different in thickness, the insulating film separating, from the channel region or a semiconductor layer, the silicon nitride film having the surface that is substantially parallel to the surface of the gate insulting film; (8) writing and erasing operations of a memory element is carried out by a word line; (9) no electrode (word line) having a function of assisting the writing and erasing operations is provided on the memory functioning member; and (10) areas right under the memory functioning members and adjacent to the diffusion region respectively have high concentrations of impurity that is of the other conductivity type than the conductivity type of the diffusion region. The memory element (devices) is, however, only required to satisfy at least one of the requirements.

An especially preferable combination of the requirements is, for example, a combination of (3) the insulating body, especially the silicon nitride film has the function of holding charges in each memory functioning member; (6) the silicon nitride film inside the memory functioning member overlaps on the diffusion region; and (9) no electrode (word line) having the function of assisting the writing and erasing operations is provided on the memory functioning member.

The combination of the requirements (3) and (9) is very advantageous as descried below.

To begin with, it is possible to arrange such that a bit line contact is provided closer to the memory functioning member provided on a side of the word line. Thus, data stored in memory functioning members can be maintained because the memory functioning members do not touch each other even when the memory elements (devices) get closer to each other. Therefore, the combination of the requirements (3) and (9) makes it easier to attain a finer memory element (devices). Note that in case where charge holding regions in the memory functioning member are made of a conductor, the charge holding regions interfere each other as the memory elements (devices) get closer to each other due to capacitor coupling. As a result, the data stored in the memory functioning member cannot be maintained.

Moreover, in case where the charge holding region in the memory functioning member is an insulator (for example, the silicon nitride film), there is no need of separating a memory functioning member per memory cell. For example, memory functioning members provided on both the sides of one word line and shared between/among a plurality of memory cells need not be parted for each memory cell, and may be shared between/among the plurality of memory cells sharing the word line. Because of this, there is no need of photo-etching process that is for parting the memory functioning member. Therefore, it is possible to attain a simpler manufacturing process. Furthermore, there is no need of allowing margins for positioning in the photolithography process and for film loss caused by the etching. Therefore, it is possible to arrange the memory cells to have a smaller margin between them. Thus, if the memory cells are micro-fabricated to the same extent, the arrangement in which the charge holding area is an insulator, requires a smaller occupying area for the memory cells, compared with the arrangement in which the charge holding area in the memory functioning member is a conductor (for example, a polycrystalline silicon film). Note that the arrangement in which the charge holding area in the memory functioning member is a conductor requires the photo-etching process for parting the memory functioning member per memory cell, thus requiring a margin for positioning during light-exposure and for film loss caused by the etching.

Furthermore, in the arrangement in which the charge holding area is an insulator, no electrode having a function of assisting the writing and erasing operations is provided on the memory functioning member, and thus this arrangement has a simpler structure as to its elements. On account of this, it is possible to produce the semiconductor storage device with a higher yield via production process having a less number of steps therein. Thus, it is possible to attain a semiconductor storage device in which the memory cell is easily mounted together with a transistor constituting a logic circuit or an analog circuit, and that has a low cost.

Moreover, more effective is the arrangement in which not only the requirements (3) and (9) but also the requirement (6) is satisfied. With the arrangement in which the charge holding region in the memory functioning member overlaps the diffusion region, it is possible to perform the writing and erasing operations by using a very low voltage. Specifically, it is possible to carry out the writing and erasing operations by using a voltage of 5V or less. This advantage is quite effective in designing circuits. Because it is unnecessary to generate a high voltage in this arrangement unlike a flash memory, it is possible to omit or scale down a charge-pumping circuit that requires a huge occupying area. Especially, in case where, in a logic LSI, a memory section of small capacity is provided, for adjustment, a periphery circuit for driving a memory cell dominates in an occupying area of the memory section, rather than the memory cell. Therefore, for attaining a smaller chip size, it is most effective to omit or scale down a voltage-boosting circuit used for the memory cell.

On the other hand, in case where the requirement (3) is not satisfied, that is, where in the memory functioning member a section for holding charges is a conductor, it is possible to carry out the writing operation,. even if the requirement (6) is not satisfied, that is, even if the conductor in the memory functioning member does not overlap the diffusion region. This is because the writing operation is assisted by capacitor coupling between (i) the conductor in the memory functioning member and (ii) the gate electrode. Moreover, in case where the requirement (9) is not satisfied, that is, where an electrode having the function of assisting the writing and erasing operations is provided on the memory functioning member, it is possible to perform the writing operation, even if the requirement (6) is not satisfied, that is, even if the conductor in the memory functioning member does not overlap on the diffusion region.

In the present semiconductor storage device, one of or both of the memory elements (devices) may be connected with a transistor. Further, the memory elements (devices) may be mounted, on one chip, together with a logic transistor. In those arrangements, the semiconductor storage device, especially, the memory element can be produced in a step that is highly compatible with a formation process of a standard transistor such as the transistor, the logic transistor, or the like. Thus, it is possible to form (i) the semiconductor device, especially the memory element, and (ii) the transistor or the logic transistor, in the same step. Therefore, it is possible to employ a very simple process in order to mount, on one chip, (i) the memory element and (ii) the transistor or the logic transistor. Thus, it is possible to attain, at a low cost, a device on which (i) the memory element and (ii) the transistor or the logic transistor are mounted together.

The present semiconductor storage device is so arranged that the memory element is capable of storing data of binary or more in each memory functioning member, and the memory element thereby stores quaternary or more. Note that the memory element may store binary data. Moreover, the memory element may have a function as a memory cell that acts as both a selection transistor and a memory by utilizing variable resistance property of the memory functioning member.

The present semiconductor storage device, by being combined with a logic element or a logic circuit, can be used in electronic apparatuses as follows: (1) data processing systems for personal computers, notebook-type computers, laptop-type computers, personal digital assistants/personal communicators, minicomputers, work stations, mainframes, multiprocessor computers, any others types of computers, and the like; (2) electronic parts constituting data processing systems for CPUs, memories, data storage devices, and the like; (3) communication apparatuses such as telephones, PHSs (devices for the personal handy-phone system), modems, routers, and the like; (4) image display apparatuses such as display panels, projectors and the like; (5) offices machines such as printers, scanner, photocopying machines; (6) imaging apparatuses such as video cameras, digital cameras, and the like; (7) entertainment/amusement apparatuses such as game machines, music players, and the like; (8) information apparatuses such as portable information terminals, watches/clocks, electronic dictionaries, and the like; (9) apparatus for use in automobiles, such as car navigation system devices, car audio devices, and the like; (10) audiovisual apparatuses for recording/reproducing data for moving pictures, still pictures, music (sounds) and the like; (11) electric appliances such as washing machines, microwave ovens, refrigerators, rice cookers, dish washers, cleaners, air conditioners, and the like; (12) apparatuses for health care, such as massaging apparatuses, weighing machines, blood-pressure meters, and the like; (13) portable storage devices such as IC cards, memory cards and the like; (14) and the like. Especially, the present semiconductor storage device is effectively applicable in portable electronic apparatuses such as portable telephones, portable information terminals, IC cards, memory cards, portable computers, portable game machines, digital cameras, portable moving-picture players, portable music players, electronic dictionaries, watches, and the like. Note that the present semiconductor storage device may be built, as at least part of a control circuit or a data storage circuit, in the electronic apparatuses, or may be detachably provided to the electronic apparatuses.

[Embodiment 1]

A semiconductor storage device of the present embodiment includes a memory element 1 as shown in FIG. 1.

The memory element 1 is arranged such that a gate electrode 104 is formed via a gate insulating film 103 on a P-type well region 102 which is formed on the surface of a semiconductor substrate 101. On the upper surface and side surfaces of the gate electrode 104, arranged is a silicon nitride film 109 which is a charge holding film, holding charges at a trap level. The portions of the silicon nitride film 109 on the both side walls serve as memory functional sections 105 a and 105 b where charges are actually held. Here, the memory functional section indicates a section where charges are actually accumulated by rewriting operation in a memory functioning member or a charge holding film. In the P-type well region 102 on the opposite sides of the gate electrode 104, formed are N-type diffusion regions 107 a and 107 b which function as source region or drain region. The diffusion regions 107 a and 107 b have an offset structure. That is, neither the diffusion regions 107 a nor 107 b extend to an region 121 under the gate electrode 104, and offset regions 120 under the charge holding film constitutes a part of the channel region.

Note that, the memory functional sections 105 a and 105 b substantially holding charges are portions on the both side walls of the gate electrode 104. Therefore, only the regions corresponding to these portions should include the silicon nitride film 109 formed thereon (see FIG. 2(a)). The memory functional sections 105 a and 105 b may have a structure in which fine particles 111 each realized by a nanometer-size electric conductor or semiconductor are dispersed in an insulating film 112 (see FIG. 2(b)). At this moment, the fine particle 111 having a diameter of less than 1 nm, which produces too large quantum effects, makes it difficult that a charge tunnels through a dot. However, the fine particle 111 having a diameter of more than 10 nm do not produce significant quantum effects at room temperature. Therefore, it is preferable that the fine particle 111 is in the 1 nm to 10 nm diameter range. Moreover, the silicon nitride film 109, a charge holding film, may be formed in a sidewall-spacer manner on the side surfaces of the gate electrode (see FIG. 3).

A principle of the writing operation by a memory element will be described with reference to FIG. 3 and FIG. 4. Note that, the following description is given based on the case where both of first memory functioning member 131 a and second memory functioning member 131 b have functions of holding charges. Writing operation indicates an operation of injecting electrons into the memory functioning members 131 a and 131 b when the memory element is a N-channel type memory element. The following description assumes that the memory element is a N-channel type memory element.

For injection (writing) of electrons into the second memory functioning member 131 b, assume that an N-type first diffusion region 107 a is a source electrode, and an N-type second diffusion region 107 b is a drain electrode, as shown in FIG. 3. For example, a voltage of 0 V is applied to the N-type first diffusion region 107 a and the P-type well region 102, a voltage of +5V is applied to the N-type second diffusion region 107 b, and a voltage of +5V is applied to the gate electrode 104. Under such voltage conditions, an inversion layer 226 extends from the first diffusion region 107 a (source electrode), but it does not reach the second diffusion region 107 b (drain electrode), which causes a pinch-off point. Electrons are accelerated from the pinch-off point to the second diffusion region 107 b (drain electrode) with the application of a high electric field, thus turning to so-called hot electrons (high-energy conduction electrons). These hot electrons are injected into the second memory functioning member 131 b, whereby writing operation is carried out. Note that, no hot electrons occur near the first memory functioning member 131 a, hence writing operation is not carried out.

Meanwhile, for injection (writing) of electrons into the first memory functioning member 131 a, assume that the second diffusion region 107 b is a source electrode, and the first diffusion region 107 a is a drain electrode, as shown in FIG. 4. For example, a voltage of 0V is applied to the second diffusion region 107 b and the P-type well region 102, a voltage of +5V is applied to the first diffusion region 107 a, and a voltage of +5V is applied to the gate electrode 104. Thus, places between source region and drain region is changed from the places in the case when electrons are injected into the second memory functioning member 131 b, whereby electrons are injected into the first memory functioning member 131 a, thus carrying out writing operation.

Next, the following will describe a principle of erasing operation in the memory element with reference to FIG. 5 and FIG. 6.

In the first erasing method of erasing information stored in the first memory functioning member 131 a, as shown in FIG. 5, a positive voltage (for example, +5V) is applied to the first diffusion region 107 a, and a voltage of 0V is applied to the P-type well region 102 so that a p-n junction between the first diffusion region 107 a and the P-type well region 102 is reverse biased, and further, a negative voltage (for example, −5V) is applied to the gate electrode 104. At this moment, because of application of the negative voltage to the gate electrode, a potential gradient especially becomes steep in the vicinity of the gate electrode. 104 of the p-n junction. Therefore, hot holes (high-energy positive holes) are induced in the P-type well region 102 of the p-n junction by band-to-band tunneling. The hot holes are attracted in the direction of the gate electrode 104 having negative potential, which results in hole injection in the first memory functioning member 131 a. In this manner, erasing operation in the first memory functioning member 131 a is carried out. In this case, it is safe that a voltage of 0V may be applied to the second diffusion region 107 b.

For erasing of information stored in the second memory functioning member 131 b, it is safe that potentials are changed between the first diffusion region and the second diffusion region in the above first method. In the second erasing method of erasing information stored in the first memory functioning member 131 a, as shown in FIG. 6, a positive voltage (for example, +4V) is applied to the first diffusion region 107 a, a voltage of 0V is applied to the second diffusion region 107 b, a negative voltage (for example, −4V) is applied to the gate electrode 104, and a positive voltage (for example, +0.8V) is applied to the P-type well region 102. At this moment, a forward voltage is applied between the P-type well region 102 and the second diffusion region 107 b, causing electrons to be injected into the P-type well region 102. The injected electrons are diffused to the p-n junction between the P-type well region 102 and the first diffusion region 107 a and then accelerated with the application of a strong electric field, thus turning to hot electrons. These hot electrons causes electron-hole pairs generated at the p-n junction. That is, application of a forward voltage between the P-type well region 102 and the second diffusion region 107 b causes electrons injected into the P-type well region 102 to trigger the generation of hot holes at the p-n junction located on the opposite side. The hot holes generated at the p-n junction are attracted in the direction of the gate electrode 104 having negative potential, which results in hole injection in the first memory functioning member 131 a.

According to the method, at the p-n junction between the P-type well region and the first diffusion region 107 a, even when a voltage insufficient for the induction of hot holes by band-to-band tunneling is applied, the electrons injected from the second diffusion region 107 b trigger the generation of electron-hole pairs at the p-n junction, thus generating hot holes. This makes it possible to decrease a voltage during the erasing operation. Especially, if there exists an offset region 120 (see FIG. 1), the gate electrode to which a negative potential is applied reduces the effect of providing a sharp p-n junction. This has a difficulty of inducing hot holes by band-to-band tunneling; however, the second method compensates for this drawback, thus realizing erasing operation at a low voltage.

Note that, for erasing of information stored in the first memory functioning member 131 a, the first erasing method requires a voltage of +5V applied to the first diffusion region 107 a. However, in the second erasing method, a voltage of +4V is enough for the erasing. Thus, according to the second erasing method, it is possible to decrease a voltage during the erasing operation, so that power consumption is reduced, thus suppressing deterioration of the memory element caused by hot carries.

Moreover, the both erasing methods are less prone to causing overerase phenomenon. The overerase phenomenon is a phenomenon in which as the amount of positive holes accumulated in a memory functioning member increases, a threshold value decreases without saturating. For EEPROM typified by flash memory, the overerase phenomenon is a big problem and causes such a fatal malfunction that selection of memory cell is impossible especially when the threshold value becomes negative. On the other hand, in the memory element of the present semiconductor storage device, a large amount of positive holes accumulated in the memory functioning member only induces electrons under the memory functioning member and has little influence on the potential of the channel region under the gate insulating film. The threshold value during the erasing operation is determined depending on the potential under the gate insulating film, thus it is more likely that no overerase phenomenon occurs.

Furthermore, the following will describe a principle of read-out operation in the memory element with reference to FIG. 7.

For read-out of information stored in the first memory functioning member 131 a, a transistor is activated under the condition where the first diffusion region 107 a is a source electrode, and the second diffusion region 107 b is a drain electrode. For example, a voltage of 0V is applied to the first diffusion region 107 a and the P-type well region 102, a voltage of +1.8V is applied to the second diffusion region 107 b, and a voltage of +2V is applied to the gate electrode 104. At this moment, when electrons are not accumulated in the first memory functioning member 131 a, a drain current is more likely to flow. On the other hand, when electrons are accumulated in the first memory functioning member 131 a, an inversion layer is less prone to being generated in the vicinity of the first memory functioning member 131 a, so that a drain current is less prone to flowing. Therefore, it is possible to read out information stored in the first memory functioning member 131 a by detecting a drain current. Especially, in the case where information is read out with the application of such a voltage that would effect pinch-off operation, the state of charges accumulated in the first memory functioning member 131 a can be judged with higher accuracy regardless of the presence or absence of charges accumulated in the second memory functioning member 131 b.

For read-out of information stored in the second memory functioning member 131 b, a transistor is activated under the condition where the second diffusion region 107 b is a source electrode, and the first diffusion region 107 a is a drain electrode. For example, it is safe that a voltage of 0V is applied to the second diffusion region 107 b and the P-type well region 102, a voltage of +1.8V is applied to the first diffusion region 107 a, and a voltage of +2V is applied to the gate electrode 104. Thus, places between source region and drain region are changed from the places in the case when information stored in the first memory functioning member 131 a is read out, whereby it is possible to read out information stored in the second memory functioning member 131 b.

Note that, when there remains a channel region (offset region 120) not covered by the gate electrode 104, an inversion layer is erased or generated depending on the presence or absence of surplus charges in the memory functioning members 131 a and 131 b. As a result of this, a large hysteresis (change in threshold value) can be obtained. Note that, too much width of the offset region 120 causes a considerable decrease in the amount of drain current and a dramatic decrease in read-out speed. Therefore, it is preferable to determine a width of the offset region 120 so that sufficient hysteresis and read-out speed can be obtained.

In the case where the diffusion regions 107 a and 107 b reach the edges of the gate electrode 104, that is, in the case where the diffusion regions 107 a and 107 b overlap the gate electrode 104, a transistor exhibits little change in threshold value by writing operation, but exhibits a dramatic change in parasitic resistance at the edges of the source and drain regions, decreasing the amount of drain current (decreasing by one or more orders of magnitude). Therefore, read-out can be carried out by detecting a drain current, and it is possible to obtain functions serving as a memory. Note that, when larger hysteresis effect is required, it is preferable that the diffusion regions 107 a and 107 b do not overlap the gate electrode 104 (the offset regions 120 exist).

By the above operating methods, one transistor can selectively carry out 2-bit writing and erasing. Memory elements are arranged such that a word line WL, a first bit line BL1, and a second bit line BL2 are respectively connected to the gate electrode 104, the first diffusion region 107 a, and the second diffusion region 107 b in the memory element, thereby making up a memory cell array.

Moreover, in the above operating methods, a changing of places between source electrode and drain electrode realizes 2-bit writing and erasing in one transistor. However, places of the source electrode and drain electrode may be fixed so that the transistor can operate as one bit of memory. In this case, one of the source region and the drain region can be a common fixed voltage, thereby halving the number of bit lines connected to the source region and the drain region.

As is clear from the above description, in a memory element of the present semiconductor storage device, memory functioning members are provided independently from the gate insulating film and provided on the opposite sides of the gate electrode, so that 2-bit operations are possible. Further, since the memory functioning members are isolated from each other by the gate electrode, interference between them during writing operation is effectively suppressed. Still further, since the gate insulating film is isolated from the memory functioning members, the thickness of the memory functioning members is reduced, thereby suppressing a short channel effect. This facilitates realization of a finer memory element, and by extension, realization of a finer semiconductor storage device.

[Embodiment 2]

A memory element in a semiconductor storage device of the present embodiment, as shown in FIG. 8, has substantially the same arrangement as that of the memory element 1 in FIG. 1, except for the arrangement in which each memory functioning members 261 and 262 is constituted by a region where charges are held (this region is a region where charges are accumulated and may be a film having a function of holding charges) and a region where charges are less prone to escaping (this region may be a film having a function of making charges less prone to escaping).

In terms of improvement in holding property of memory, the memory functioning members preferably include an insulating film and a charge holding film capable of holding charges. In the present embodiment, a silicon nitride film 242 having a level of trapping charges is used as a charge holding film, and silicon oxide films 241 and 243 capable of preventing the dissipation of charges accumulated in the charge holding film are used as insulating films. The memory functioning member including the charge holding film and the insulating films prevents the dissipation of charges, thereby improving holding property. Moreover, as compared to the constitution of the memory functioning member including the charge holding film alone, the above constitution of the memory functioning member can reduce the volume of the charge holding film to an appropriately small volume, and can restrict transfer of charges inside the charge holding film, thereby suppressing changes of properties caused by the transfer of charges during memory holding. Further, the structure in which the silicon nitride film 242 is sandwiched between the silicon oxide films 241 and 243 enhances a charge injection efficiency during rewriting operation, thus allowing for a higher-speed operation. Note that, in this memory element, the silicon nitride film 242 may be substituted with a ferroelectric substance.

The regions where charges are held (silicon nitride film 242) in the memory functioning members 261 and 262 overlap diffusion regions 212 and 213, respectively. To “overlap” means that at least a part of the region where charges are held (silicon nitride film 242) exists above at least a part of each of the diffusion regions 212 and 213. Note that, reference numeral 211 represents a semiconductor substrate, reference numeral 214 represents a gate insulating film, reference numeral 217 represents a gate electrode, reference numeral 271 represents an offset region of the gate electrode 217 and each of the diffusion regions 212 and 213. An upper surface of the semiconductor substrate 211 beneath the gate insulating film 214 is a channel region (not shown). The following will describe effects brought by the arrangement where the silicon nitride films 242, which are regions where charges are held in the memory functioning members 261 and 262, overlap the diffusion regions 212 and 213.

As shown in FIG. 9, in the periphery of the memory functioning member 262, when the amount of offset between the gate electrode 217 and the diffusion region 213 is W1, and a width of the memory functioning member 262 in a cross section in the channel length direction of the gate electrode is W2, the amount of overlap between the memory functioning member 262 and the diffusion region 213 is expressed by W2−W1. Here, it is important that the part including the silicon nitride film 242 in the memory functioning member 262 overlaps the diffusion region 213, that is, the relation W2>W1 is satisfied.

In FIG. 9, a width of the memory functioning member 262 is denoted by W2 because the edge of the silicon nitride film 242 on the side distant from the gate electrode 217 matches the edge of the memory functioning member 262 on the side distant from the gate electrode 217. However, as shown in FIG. 10, when the edge of the silicon nitride film 242 a on the side distant from the gate electrode does not match the edge of the memory functioning member 262 a on the side distant from the gate electrode, W2 should be defined as the distance from the edge of the gate electrode to the edge of the silicon nitride film 142 a on the side distant from the gate electrode.

FIG. 11 shows a drain current Id with changes in the amount of offset W1 when the width W2 of the memory functioning member 262 is fixed to 100 nm in a structure of the memory element in FIG. 9. Here, values of the drain current were obtained by a device simulation under the condition where the memory functioning member 262 is in an erased state (includes holes accumulated therein) and the diffusion regions 212 and 213 are source electrode and drain electrode, respectively. As is apparent from FIG. 11, when W1 is 100 nm or more (that is, the silicon nitride film 242 does not overlap the diffusion region 213), the drain current decreases rapidly. The value of the drain current is appropriately in proportion to a read-out speed. Therefore, when W1 is 100 nm or more, the performance of memory is rapidly degraded. On the other hand, when W1 is a value in the range where the silicon nitride film 242 overlaps the diffusion region 213, the drain current decreases moderately. Therefore, considering that variations in mass production process, if at least a part of the silicon nitride film 242, which is a film capable of holding charges, does not overlap the source region and drain region, it is practically difficult to obtain memory function.

In view of the result of the above-mentioned device simulation, memory cell arrays with W1 of 60 nm and 100 nm as design value were prepared under the condition where W2 is fixed to 100 nm. When W1 is 60 nm, there is an overlap of 40 nm as a design value between the silicon nitride film 142 and the diffusion regions 212 and 213. When W1 is 100 nm, there is no overlap between them. When comparing to results of a read-out time measurement between these memory cell arrays in the worst cases considering variations, the memory cell array with W1 of 60 nm reads at a speed of 100 times faster in a read-out access time than the memory cell array with W1 of 100 nm. Practically, a read-out access time is preferably 100 nanoseconds or less per bit; however, when W1=W2, it is impossible to achieve this condition. In view of variations in manufacturing process, (W2−W1)>10 nm is more preferable.

For read-out of information stored in the memory functioning member 261 (region 281), as in the case of Embodiment 1, it is preferable that the diffusion region 212 and the diffusion region 213 are source electrode and drain region, respectively, and a pinch-off point is formed in the channel region, at a point closer to the drain region. That is, in reading out information stored in one memory functioning member of two memory functioning members, a pinch-off point is preferably formed in the channel region, in a region closer to the other memory functioning member. This makes it possible to detect information stored in the memory functioning member 261 at a good sensitivity regardless of storage conditions in the memory functioning member 262. This is a great factor for the realization of two-bit operation.

On the other hand, when information is let stored in only one memory functioning member of two memory functioning members, or when the two memory functioning members are used with the same storage conditions, the formation of a pinch-off point is not always needed for read-out operation. Note that, it is preferable that a well region (for N channel element, P-type well), not shown in FIG. 8, is formed on the surface of the semiconductor substrate 211. The formation of a well region facilitates control of other electric properties (property of withstanding voltage, junction capacitance, short channel effect) while optimizing impurity concentration in the channel region for memory operations (writing operation and read-out operation).

It is preferable that the memory functioning member includes a charge holding film arranged substantially parallel to the surface of the gate insulating film. In other words, it is preferable that the upper surface of the charge holding film in the memory functioning member is arranged so as to be located at a place a given distance from the upper surface of the gate insulating film. Specifically, as shown in FIG. 12, the silicon nitride film 242 a, which is a charge holding film in the memory functioning member 262, has a surface substantially parallel to the surface of the gate insulating film 214. In other words, it is preferable that the silicon nitride film 242 a is formed at a uniform height from the level corresponding to the surface of the gate insulating film 214.

Existence of the silicon nitride film 242 a which is substantially parallel to the surface of the gate insulating film 214 in the memory functioning member 262 can effectively control the tendency of forming an inversion layer in the offset region 271 by the amount of charges accumulated in the silicon nitride film 242 a, and by extension can enhance a memory effect. Further, the arrangement in which the silicon nitride film 242 a is substantially parallel to the surface of the gate insulating film 214 can reduce a change of memory effect to a relatively small change even when the amount of offset (W1) varies, thus suppressing varying degrees of memory effect. In addition, it is possible to suppress upward transfer of charges in the silicon nitride film 242 a and to prevent changes in properties during memory holding, caused by transfer of charges.

Further, it is preferable that the memory functioning member 262 includes the insulating film (For example, a portion in the silicon oxide film 244 on the offset region 271) isolating the silicon nitride film 242 a, which is substantially parallel to the surface of the gate insulating film 214, from the channel region (or well region). This insulating film prevents the dissipation of charges accumulated in the charge holding film, thus attaining a memory element having a much better holding property.

Note that, by controlling a film thickness of the silicon nitride film 242 a and by controlling a film thickness of the insulating film (a portion of the silicon oxide film 244 above the offset region 271) beneath the silicon nitride film 242 a to uniform thickness, it is possible to maintain a distance from the surface of the semiconductor substrate to charges accumulated in the charge holding film to a substantially uniform distance. That is, a distance from the surface of the semiconductor substrate to charges accumulated in the charge holding film can be controlled to a distance value between a minimum value of film thickness of the insulating film beneath the silicon nitride film 242 a and a sum of a maximum value of film thickness of the insulating film beneath the silicon nitride film 242 a and a maximum value of film thickness of the silicon nitride film 242 a. This makes it possible to control a density of electric flux lines caused by charges accumulated in the silicon nitride film 242 a and to extremely reduce varying degrees of memory effect of the memory element.

[Embodiment 3]

As shown in FIG. 13, a memory functioning member 262 in the semiconductor storage device of the present embodiment includes a silicon nitride film 242, which is a charge holding film, with substantially uniform film thickness, having a region 281 which is arranged substantially parallel to the surface of the gate insulating film 214 and a region 282 which is arranged substantially parallel to the side surface of the gate electrode 217.

When a positive voltage is applied to a gate electrode 217, an electric flux line 283, as indicated by arrow, in a memory functioning member 262 passes through the silicon nitride film 242 twice (the region 282 and the region 281). Note that, when a negative voltage is applied to the gate electrode 217, an electric flux line reverses its direction. Here, the silicon nitride film 242 has a relative permittivity of approximately 6, and the silicon oxide films 241 and 243 have a relative permittivity of approximately 4. This arrangement of the present embodiment can make an effective relative permittivity in the direction of the electric flux line larger and make difference in potential between both ends of the electric flux line smaller than the arrangement in which the region 281 alone exists in the charge holding film. That is, a large part of the voltage applied to the gate electrode 217 is used to strengthen an electric field in the offset region 271.

Injection of charges into the silicon nitride film 242 during rewriting operation occurs because generated charges are attracted by an electric filed in the offset region 271. Therefore, inclusion of the charge holding film indicated by the arrow 282 increases the amount of charges injected into the memory functioning member 262 during rewriting operation, thus increasing a rewriting speed. Note that, if the part corresponding to the silicon oxide film 243 is also a silicon nitride film, that is, the charge holding film is not at a uniform height with respect to the level of the surface of the gate insulating film 214, upward transfer of charges in the silicon nitride film becomes pronounced, resulting in degrading of holding property.

It is more preferable that the charge holding film is made up of dielectric material such as hafnium oxide having a very high relative permittivity, instead of silicon nitride film. Further, it is preferable that the memory functioning member further includes an insulating film (a portion in the silicon oxide film 241 above the offset region 271) isolating the charge holding film, which is substantially parallel to the surface of the gate insulating film, from a channel region (or well region). This insulating film prevents the dissipation of charges accumulated in the charge holding film, further enhancing holding property.

Moreover, it is preferable that the memory functioning member further includes an insulating film (a portion of the silicon oxide film 241 in contact with the gate electrode 217) isolating the gate electrode from the charge holding film extending substantially parallel to the side surface of the gate electrode. This insulating film prevents change in electric properties caused by injection of charges from the gate electrode to the charge holding film, thus enhancing reliability of a memory element. Further, as in the case of Embodiment 2, it is preferable that a film thickness of an insulating film (a portion of the silicon oxide film 241 above the offset region 271) beneath the silicon nitride film 242 is controlled to a uniform thickness, and a film thickness of an insulating film (a portion of the silicon oxide film 241 in contact with the gate electrode 217) arranged on the side surface of the gate electrode is controlled to a uniform thickness. This makes it possible to generally control a density of electric flux lines which are caused by charges accumulated in the silicon nitride film 242 and to prevent leakage of charges.

[Embodiment 4]

In the present embodiment, the following will describe optimization of a length of a gate electrode, a distance between memory functioning members, and a distance between a source region and a drain region in a memory element of a semiconductor storage device.

As shown in FIG. 14, A denotes a length of a gate electrode in a cross section in the channel length direction, B denotes a distance (channel length) between a source region and a drain region, and C denotes a distance from the edge of one memory functioning member to the edge of the other memory functioning member, that is, a distance from the edge of a film capable of holding charges in one memory functioning member in a cross section in the channel length direction (the edge of the film which is distant from the gate electrode) to the edge of a film capable of holding charges in the other memory functioning member (the edge of the film which is distant from the gate electrode).

In such a memory element, B<C is preferable. By satisfying such a relation, there exists offset regions 271 between a part of the channel region located beneath the gate electrode 217 and a diffusion region 212 and between the part of the channel region located beneath the gate electrode 217 a and a diffusion region 213. With this arrangement, in all of the offset regions 271, easiness of inversion effectively varies depending on charges accumulated in the memory functioning members 261 and 262 (silicon nitride films 242). This causes enhancement in memory effect and especially realizes speedup of read-out operation.

When there exists offsets between the gate electrode 217 and the diffusion region 212 and between the gate electrode 217 and the diffusion region 213, that is, when A<B, easiness of inversion in the offset regions when a voltage is applied to the gate electrode drastically varies depending on the amount of charges accumulated in the memory functioning members, thus realizing enhancement in memory effect, and especially reduction in short channel effect.

Incidentally, existence of the offset regions 271 is not always needed as long as memory effect shows up. In the case where the offset regions 271 do not exist, if impurity concentration in the diffusion regions 212 and 213 is low enough, memory effect can show up in the memory functioning members 261 and 262 (silicon nitride films 242). In view of this, A<B<C is the most preferable relation.

[Embodiment 5]

As shown in FIG. 15, a memory element in a semiconductor storage device of the present embodiment has substantially the same arrangement as that of the memory element in Embodiment 2, except for the arrangement in which the semiconductor substrate in Embodiment 2 is replaced with an SOI substrate.

This memory element has an arrangement in which an embedded oxide film 288 is formed on a semiconductor substrate 286, and an SOI layer is further formed thereon. The SOI layer includes diffusion regions 212 and 213 and a body region 287 which is a region except for the diffusion regions 212 and 213 in the SOI layer.

This memory element can bring about the same effect as that of the memory element in Embodiment 2. Moreover, this memory element can significantly reduce the amount of junction capacitance of the diffusion regions 212 and 213 and the body region 287, thus allowing for speedup of a device and lower power consumption.

[Embodiment 6]

As shown in FIG. 16, a memory element in a semiconductor storage device of the present embodiment has substantially the same arrangement as that of the memory element in Embodiment 2, except for the arrangement in which P-type high concentration regions 291 are additionally provided adjacent to ends of N-type diffusion regions 212 and 213 facing a channel region. More specifically, concentration of impurity giving a P-type nature (for example, boron) to the P-type high concentration regions 291 is higher than that of impurity giving a P-type nature to a region 292. Suitable P-type impurity concentration in the P-type high concentration regions 291 is, for example, in the order of 5×1017 cm to 1×1019 cm-3. Also, P-type impurity concentration in the region 292 can be, for example, 5×1016 cm to 1×1018 cm-3.

*95 Thus, provision of the P-type high concentration regions 291 causes a sharp junction of the diffusion regions 212 and 213 and a semiconductor substrate 211 directly beneath the memory functioning members 261 and 262. Therefore, hot carriers are more likely to generate during writing and erasing operations, allowing for decrease in voltage for writing and erasing operations or speedups of writing and erasing operations. Further, a relatively low impurity concentration in the region 292 causes a low threshold value when memory is in a state of being erased, thus increasing the amount of drain current. This increases a read-out speed. Therefore, it is possible to obtain a memory element with a low rewriting voltage or a high rewriting speed, and a high read-out speed.

In FIG. 16, provision of the P-type high concentration regions 291 beneath. the memory functioning members (that is, not directly beneath the gate electrode) in the vicinity of a source region and a drain region remarkably increases a threshold value of the entire transistor. An extent of this increase is remarkably larger than that in the case where there are the P-type high concentration regions 291 directly beneath the gate electrode. When writing charges (electrons in a case where the transistor is N-channel type transistor) are accumulated in the memory functioning member, the difference between the threshold values become much larger. On the other hand, when enough erasing charges (positive holes in a case where the transistor is N-channel type transistor) are accumulated in the memory functioning member, a threshold value of the entire transistor drops to a threshold value determined depending on impurity concentration in the channel region (region 292) beneath the gate electrode. That is, a threshold value during erasing operation does not depend on impurity concentration in the P-type high concentration regions 291, whereas a threshold value during writing operation is significantly affected by impurity concentration in the P-type high concentration regions 291. Therefore, arrangement of the P-type high concentration regions 291 beneath the memory functioning members in the vicinity of the source region and drain region remarkably varies only a threshold value during writing operation, thus allowing for significant enhancement in memory effect (difference in threshold value between writing operation and erasing operation).

[Embodiment 7]

As shown in FIG. 17, a memory element in a semiconductor storage deice of the present embodiment has substantially the same arrangement as that of the memory element in Embodiment 2, except for the arrangement in which a thickness (T1) of an insulating film isolating a charge holding film (silicon nitride film 242) from a channel region or well region is smaller than a thickness (T2) of a gate insulating film.

With the demand for the property of withstanding voltage during writing operation of memory, the gate insulating film 214 has a lower limit of the thickness T2. However, the thickness T1 of the insulating film can be smaller than the thickness T2, regardless of the demand for the property of withstanding voltage.

In this memory element, as described above, a high degree of flexibility in the thickness T1 results from the following grounds.

That is, in this memory element, the insulating film isolating a charge holding film from the channel region or the well region is not sandwiched between the gate electrode and the channel region or well region. Therefore, the insulating film isolating the charge holding film from the channel region or well region is not directly effected not by a high electric field between the gate electrode and the channel region or the well region, but is effected by a relatively weak electric filed extending from the gate electrode in the lateral direction. Therefore, regardless of the demand for the property of withstanding voltage with respect to the gate insulating film, the thickness T1 can be smaller than the thickness T2.

Reduction of the thickness T1 facilitates injection of charges into the memory functioning members, thus allowing for decrease in voltage during writing and erasing operations or speedups of writing and erasing operations. Also, reduction of the thickness T1 increases the amount of charges induced in the channel region or well region when charges are accumulated in the silicon nitride film 242, thus allowing for enhancement in memory effect.

By the way, among electric flux lines in the memory functioning members, there is a short one, as indicated by an arrow 284 in FIG. 13, that does not pass through the silicon nitride film 242. An electric field intensity on such a short electric flux line is relatively high, so that an electric field along this electric flux line plays a large role in writing operation. Reduction of the thickness T1 causes the silicon nitride film 242 to move downward in the drawing, so that the electric flux line indicated by the arrow 283 can pass through the silicon nitride film. This causes a high effective relative permittivity in the memory functioning member along the electric flux line 284, thus allowing for a smaller difference in potential between both ends of the electric flux line. Therefore, a large part of voltage applied to the gate electrode 217 is used to strengthen an electric field in the offset region, thus permitting speedups of writing and erasing operations.

On the contrary, in EEPROM typified by a flash memory, for example, an insulating film isolating a floating gate from a channel region or well region is sandwiched between a gate electrode (control gate) and the channel region or well region, so that the insulating film is directly effected by a high electric field from the gate electrode. Therefore, in the EEPROM, a thickness of the insulating film isolating the floating gate from the channel region or well region is limited, which inhibits the optimization for the functions of the memory element.

As is obvious from the above description, the relation T1<T2 allows for decrease in voltage during writing and erasing operations or speedups of writing and erasing operations, without decrease in voltage resisting performance of memory and further allows for enhancement in memory effect.

Note that, it is more preferable that the thickness T1 of the insulating film is 0.8 nm or more at which uniformity and film quality of the insulating film in manufacturing process can be maintained to a certain level, and which is a limit at which holding property does not degrade to an extreme.

Specifically, for a liquid crystal driver LSI with a large design rule which requires a high withstand voltage, a maximum voltage 15V to 18V is required to drive a liquid crystal panel TFT. Because of this, it is usually impossible to reduce the thickness of a gate oxide film. When a nonvolatile memory of the present embodiment for image control-use is mixed into the liquid crystal driver LSI, in the memory element of the present invention, it is possible to design a suitable thickness of the insulating film insulating a charge holding film (silicon nitride film 242) from the channel region or well region, independently from the thickness of the gate insulating film. For a memory cell with a gate electrode length (word line width) of 250 nm, for example, T1=20 nm and T2=10 nm can be set individually, thus realizing a memory cell of an excellent efficiency of writing. (The reason why no short channel effect occurs with the thickness T1 that is larger than that of an ordinary logic transistor is that a source region and a drain region are offset from the gate electrode.)

[Embodiment 8]

As shown in FIG. 18, a memory element in a semiconductor storage device of the present embodiment has substantially the same arrangement as that of the memory element in Embodiment 2, except for the arrangement in which a thickness (T1) of an insulating film isolating a charge holding film (silicon nitride film 242) from a channel region or well region is larger than a thickness (T2) of a gate insulating film.

For a requirement for the prevention of short channel effect of a device, a gate insulating film 214 has an upper limit of its thickness T2. However, the thickness T1 of the insulating film can be larger than the thickness T2, regardless of the requirement for the prevention of short channel effect. That is, for the development of scaling down (the development of reduction in thickness of the gate insulating film), a thickness of an insulating film isolating the charge holding film (silicon nitride film 242) from the channel region or well region can be designed suitably, independently from a thickness of the gate insulating film. This brings about the effect that the memory functioning members do not get in the way of scaling down.

In the memory element of the present embodiment, the reason for a high degree of flexibility in the thickness T1 is, as described above, that the insulating film isolating the charge holding film from the channel region or well region is not sandwiched between the gate electrode and the channel region or well region. Therefore, the thickness T1 can be larger than the thickness T2, regardless of the requirement for the prevention of short channel effect with respect to the gate insulating film. Increase in thickness T1 enables the prevention of charges accumulated in the memory functioning members from scattering and improvement of holding property of memory.

Consequently, the relation T1>T2 enables improvement in holding property without degradation of short channel effect of memory.

Note that, the thickness T1 of the insulating film is preferably 20 nm or less, considering a decrease in rewriting speed.

More specifically, in a conventional nonvolatile memory typified by flash memory, a selection gate electrode constitutes a writing/erasing gate electrode, and a gate insulating film (including a floating gate) corresponding to the write-erasing gate electrode also serves as charge accumulating film. Therefore, the demand for a finer memory element (a thinner film is essential for the prevention of short channel effect) and the demand for securement of reliability (For prevention of leakage of holding charges, the thickness of an insulating film isolating the floating gate from the channel region or the well region cannot be reduced to about 7 nm or less.) are mutually contradictory, and hence, it is difficult to realize a finer memory element. Actually, according to ITRS (International Technology Roadmap for Semiconductors), a thinner physical gate length of about 0.2 micrometer or thinner is not yet in sight. However, in the memory element of the present embodiment, as described above, T1 and T2 can be designed individually, thus realizing a fine film structure.

For example, for a memory cell with a gate electrode length (word line width) of 45 nm, it is possible to realize a memory element which causes no short channel effect by individually setting the memory cell to T2=4 nm and T1=7 nm. The reason why no short channel effect occurs even when T2 is set thicker than a thickness of an ordinary logic transistor is because the source region and the drain region are offset with respect to the gate electrode. Further, in the memory element of the present embodiment, the source region and the drain are offset with respect to the gate electrode, thus further facilitating a finer memory element, as compared to an ordinary logic transistor.

That is, since an electrode for assisting writing and erasing in an upper part of the memory functioning member, the insulating film isolating the charge holding film from the channel region or the well region is not directly effected by a high electric field that acts upon between the electrode for assisting writing and erasing and the channel region or the well region, but is just effected by a relatively weak electric filed extending from the gate electrode in the lateral direction. Therefore, it is possible to realize a memory element holding a gate length as thin as or thinner than a gate length of a logic transistor in the same fabrication generation.

[Embodiment 9]

A present embodiment relates to a change in electric properties, the change being caused when a memory element is rewritten in a semiconductor storage device.

In an N-channel type memory element, a change in an amount of charge in a memory functioning member results in drain current (Id)-gate voltage (Vg) characteristics (measured values), as shown in FIG. 19.

As shown in FIG. 19, a writing operation starting from erased state (solid line) not only increases a threshold value, but also significantly decreases the gradient of the graph in a sub-threshold region. Therefore, even in a region in which the gate voltage (Vg) is relatively high, a drain current ratio between an erasing state and a writing state is large. For example, where Vg=2.5V, the current ratio is in two digits or more. This characteristic is significantly different from that of the flash memory (see FIG. 31).

The appearance of this characteristic is a unique phenomenon caused because an offset between a gate electrode and a diffusion region makes it difficult for a gate electric field to enter an offset region. When the memory element is in the writing state, it is very difficult to generate an inversion layer in the offset region under the memory functioning member, even if a positive voltage is applied on the gate electrode. This is the reason why the gradient of the Id-Vg curve is small in the sub-threshold region when the memory element is in the writing state.

On the other hand, when the memory element is in the erasing state, electrons are induced in high density in the offset region. Further, when a voltage of 0V is applied on the gate electrode (that is, when the memory element is in an off state), no induction of electrons is caused in a channel under the gate electrode (therefore, an off current is small). This is the reason why the Id-Vg curve has a large gradient in the sub-threshold region and an increasing rate (conductance) of current is large in the regions at or above the threshold value, when the memory element is in the erasing state.

As described above, the memory element constituting the semiconductor storage device of the present embodiment is capable of attaining an especially large drain current ratio between in writing and in erasing.

[Embodiment 10]

The present embodiment relates to a semiconductor storage device including a plurality of memory elements described in Embodiments 1 through 8, and relates to a redundancy circuit used in the semiconductor storage device.

The present redundancy circuit makes it possible to select redundant lines of an MOS memory element and cells associated with the redundant lines. To help understanding the present invention, the following description provides some details, such as specific address arrangements. However, it will be obvious for a person skilled in the art that these details are not prerequisites for carrying out the present invention. In other words, well-known circuits are shown in the block diagrams so as not to obscure the present invention with unnecessary details.

The circuit arrangements shown in FIGS. 20 through 22 are suitable for the semiconductor storage device using the memory elements shown in Embodiments 1 through 8. A memory including the plurality of memory elements uses a potential of approximately 5V (Vpp) to perform write/erase operation with respect to memory cells (see FIG. 3 of Embodiment 1). This high potential may be used in order to blow fuses during write/erase operation of the redundancy circuit of the present embodiment. During a non-write/non-erase period of the memory, Vpp is kept at a potential of Vcc. The circuit shown in FIG. 25 is suitable for a semiconductor storage device which uses memory elements (Embodiments 1 through 8) using write/erase potentials of Vpp.

In the present embodiment, the redundancy circuit includes a plurality of polysilicon fuses which are selectively blown to program buffers (described later).

In FIG. 20, it is assumed that the memory includes two extra redundant row lines. The row lines include memory cells used for replacing defective cells in memory array. A redundant row M is selected by an ordinary decoder 315 including NOR gates. An output of the decoder 315, the output being supplied to a signal line 310, selects the redundant row M. Likewise, an output of the decoder 316, the output being supplied to a signal line 311, selects a redundant row line N. The redundant row decoders such as the decoders 315 and 316 may be regular decoders used in such memories as row decoders 317 and 318, which select signal lines 312 and 313, respectively. The row decoders 317 and 318, and all the other regular row decoders respectively receive different combinations of row address signals ADD 1 through ADD 9 (true) and complementary address signals/ADD 1 through/ADD 9 (not). The row decoders 317 and 318 also receive output signals from the decoders 315 and 316. Thus, the signal lines 310 and 311 are connected to input terminals of the row decoders 317 and 318. If the redundant row M or N is selected, all the regular rows in the memory array are deselected. This is because a defective regular row is not selected when an address for that row is supplied to the memory.

The decoder 315 receives signals from programmable buffers 321M through 329M, and the decoder 316 receives signals from programmable buffers 321N through 329N. The buffers 321 through 329 (M, N), which are for the row decoders 315 and 316, receive different combinations of the row address signals ADD1 through ADD9 and the complementary address signals/ADD1 through/ADD9. In addition, the buffers 321M through 329M receive a/RM signal, and the buffers 321N through 329N receive a/RN signal. These signals allow for selection of buffers associated with a single decoder which is used for the purpose of programming. The/RM signal and the /RN signal are generated by the circuit of FIG. 21.

When a defective row is identified in the memory array, the buffers 321 through 329 (M, N) are programmed so as to recognize the address of the defective row. Upon receipt of this address, the buffers 321 through 329 (M, N) supply all low signals to the decoder 315. This brings a signal on a signal line 328 to low, thereby supplying a high output to the signal line 310, which selects the row M instead of the defective row. Each defective row in the memory array is replaced with a redundant row, and a sufficient number of redundant rows are supplied thereto.

If there is no defective row, or if there are more redundant rows than defective rows, it is necessary not to select unused redundant rows. Suppose, for example, that there is no defective row in the memory array, and therefore the row 310 is not selected by any address. A signal on a line 330, which is connected to the decoder 315, prevents selection of the row M. The signal line 330 is connected to a supply line of a line voltage Vpp through a fuse 331, and to the ground through a couple of transistors connected in parallel, i.e. an enhancement mode transistor 332 and a depression mode transistor 333.

The transistor 333 is relatively large, and when it conducts, draws a sufficient current from the supply line, so as to blow the fuse 331. On the other hand, the transistor 332 is relatively small as compared to the transistor 333, and when it conducts, ensures that the signal line 330 remains at a ground potential. The gate of the transistor 333 receives an RM signal. The RM signal is brought to high while the buffers 321M through 329M, which are associated with the decoder 315, are programmed. If the buffers 321M through 329M are not programmed, that is, if the row M is not to be used, the transistor 333 does not conduct. In this case, the fuse 331 remains intact, and the signal line 330 is always kept high. The high voltage on the signal line 330 causes the decoder 315 to output a low signal.

On the other hand, if the redundant row M is to be used, the buffers 321M through 329M are selected for programming. When the RM signal is high, the fuse 331 is blown, and the signal line 330 is therefore connected to the ground through the transistor 332. Therefore, a low signal on the signal line 330 is supplied to the decoder 315, which in turn outputs a high signal when an appropriate address is supplied to the buffers 321M through 329M.

The decoder 316 receives a similar signal from a signal line 334. The signal line 334 is connected to Vpp through a fuse which is blown when the RN signal is high. Similarly, the programmable circuit connected to each redundant row line includes a circuit which receives an “R” signal.

After the selection of a redundant row, the redundant row is discarded because the redundant row includes defective cells. A circuit 337 shown in FIG. 20 may be connected to a decoder so as to allow for deselection of a selected redundant row. A redundant disregard signal RD on a signal line 336 permanently keeps deselection of the decoder 316. A control signal RDS, which controls the MOS transistor 338, is generated from second address signals and a chip enable signal /CE, in a manner similar to the generation of the RM signal described below.

The signal line 336 is connected to an output terminal of an inverter including transistors 340 and 341. The gate of the transistor 341 is connected to Vpp through a fuse 342. The fuse 342 is connected to the ground through a couple of transistors 338 and 339 connected in parallel. If the fuse 342 remains intact, the transistor 341 conducts, and the signal line 336 is kept at the ground potential. This keeps the decoder 316 to operate normally.

On the other hand, if the row N is selected and found to be defective, the control signal RDS is supplied to the gate of the transistor 338, thereby blowing the fuse 342. As a result, because the transistor 341 does not conduct, the signal line 336 is connected to Vcc through the transistor 340 and is kept high. Thus, the selection of the redundant row line is prevented and another redundant row line is selected to replace a defective row line.

In the present embodiment, for the purpose of programming the redundancy circuit, Y-line addresses (e.g. bit line addresses) are used for selecting groups of programmable buffers. This allows for selection without providing extra package pins. The number of Y-line address bits required for programming is a function of the number of redundant lines in the memory. For example, if the memory includes four redundant lines, two Y-line addresses are necessary in order to select each group of buffers for programming. However, in the present embodiment, one additional Y-line address is used to provide a distinguishable programming. address for permanently disabling the programming circuit for the redundant rows.

In an arrangement where two redundant rows are used, two address signals are required. The two address signals are shown in FIG. 21 as address signals ADDy0 and ADDy1 (and complementary. address signals thereof). Different combinations of these address signals are respectively supplied to NOR gates 346, 347, and 348 so as to allow for individual selection of the NOR gates 346, 347, and 348. For example, the NOR gate 346 may be selected when the address signals ADDy0 and ADDy1 are low. The NOR gates 346, 347, and 348 receive a chip enable signal CEx through a signal line 361, and additionally receive a repair inhibit signal through a signal line 359.

The gate of an inverter 363 receives the chip enable signal /CE. An output of the inverter 363 is supplied to an inverter 364, and an output of the inverter 364 is supplied to an inverter 365. The inverter 365 supplies the chip enable signal CEx to the signal line 361. The inverter 363 is a low ratio inverter, that is, the depletion mode transistor has a large width-to-length channel ratio, while the enhancement mode transistor has a small width-to-length ratio. In order to obtain a low output from the inverter 363, the chip enable signal /CE needs to be higher than its normal potential.

Thus, in order to start programming the redundancy circuit, the chip enable signal /CE needs to be high. In this case, the inverter 363 outputs a low signal, and the inverter 364 outputs a high signal. Therefore, the inverter 365 outputs a low signal. If the chip enable signal CEx is low, outputs of the NOR gates 346, 347, and 348 are high if the other inputs are low. During normal operation of the memory, the chip enable signal /CE is high, thereby preventing programming. However, it can be ensured by other means that programming will not be executed inadvertently even if the chip enable signal /CE is above the normal potential.

In the beginning of the programming, the output of the NOR gate 348 is kept low. This prevents the transistor 353 from conducting, and connects a transistor 357 to Vpp through a fuse 355. A signal line 359 is thus kept at the ground potential, and a low signal is supplied to the NOR gates 346 and 347. Then, with an appropriate Y-address, the NOR gate 346 is selected, and the high RM signal supplied from the NOR gate 346 is outputted as a low /RM signal from an inverter 350. As shown in FIG. 20, with the RM signal high and the /RM signal low, the buffers 321M through 329M are programmed as described below, thereby blowing the fuse.

Next, when the address signal ADDy0 is low and the address signal ADDy1 is high, the high RN signal supplied from the NOR gate 347 is outputted as a low /RN signal from an inverter 351. The/RN signal allows for programming of the buffers 321N through 329N of FIG. 20.

When the address signals ADDy0 and ADDy1 are brought to low after the buffers are programmed, the output of the NOR gate 348 is brought to high. This causes the transistor 353 to conduct, thereby blowing the fuse 355. As a result, the gate of the transistor 357 is kept at the ground potential through the transistor 354, and the repair inhibit signals is fixed at Vcc through the transistor 356. Once this happens, a high signal can never be outputted from the NOR gates 346 and 347. Therefore, none of the buffers can be programmed again. This prevents a user from inadvertently programming the buffers even if the chip enable signal /CE is brought to high. Needless to say, attention must be paid in sequencing the programming operation, so to ensure that a high signal will not be supplied from the NOR gate 348 before all necessary programming is completed.

FIG. 22 illustrates a typical programmable buffer, such as the buffer 321M of FIG. 20. In the buffer 321, an address signal ADD 1 is received at the gate of a transistor 369 and at the drain of a transistor 381. A transistor 370 conducts upon application of the /RM signal to the gate, thereby connecting the gate of a transistor 372 to the ground. The gate of the transistor 372 is connected to Vpp through a depletion mode transistor 368. If the /RM signal (which selects the buffer for programming) is low while the buffer of FIG. 22 is programmed, the transistor 372 conducts, thereby blowing a fuse 371. At this time, a transistor 373 fixes a node 374 at the ground potential.

If the node 374 is at the ground potential, an inverter including transistors 375 and 376 outputs a high signal to a signal line 377, which is connected to the gate of the transistor 381. The output of the inverter is also supplied to an inverter including transistors 378 and 379. When the fuse is blown and the transistor 381 conducts due to the high output, the gate of a transistor 380 is connected to the ground through the inverter including the transistors 378 and 379. Therefore, the transistor 380 does not conduct. During operation of the memory, if the address signal ADD1 is high, the output of the buffer is high. On the other hand, if the address signal /ADD1 is high, the output of the buffer is low. Thus, if the address signal ADD1 is low, only the address signal ADD1 is low.

If the address signal ADD1 is high during the programming, the transistor 369 conducts, and the transistor 372 does not conduct. After the programming, the node 374 is kept permanently high through the fuse 371. This causes the transistor 376 to keep the signal line 377 always low. An output of a next inverter stage is high, thereby causing the transistor 380 to conduct. Then, the address signal /ADD1 is outputted through the transistor 380.

FIG. 23 illustrates another buffer. As shown in FIG. 23, a transistor 391 receives an address signal ADDx, and a transistor 392 receives an R signal. If neither the transistor 390 nor the transistor 392 conducts, the gate of a transistor 394 is connected to Vcc through the transistor 390, and is therefore high. This blows a fuse 393 in the same manner as the fuse 371 of FIG. 22. If the fuse 393 is blown, a node 401 is set to the ground potential through a transistor 395. If the node 401 is low, neither a transistor 397 nor a transistor 399 conducts, while a transistor 396 conducts and causes the gate of the transistor 398 to be high. Then, the address signal ADDx is supplied to an output line OUT through the transistor 398. On the other hand, if the fuse 393 remains intact, the node 401 is high, and the transistors 397 and 399 conduct. As a result, the transistor 398, whose gate being at the ground potential, does not conduct. The address signal /ADDx is thus supplied to the output line OUT.

During the programming of each redundant row decoder, all the address signals ADD1 through ADD9 are initially kept high, thereby preventing any fuses from being blown. When only one of the fuses are to be blown, one of the address signals is brought to low. This prevents the circuit on the memory chip from excessive current, hence from damages. To put it more simply, the rows addressed are changed from all logical ones to the address of the defective row, one address bit at a time.

Suppose that a defective row in the memory array or defective cells along a row are found, and that the address signals ADD1 through ADD9 are all binary signals. Further suppose that the redundant row M is programmed to replace the defective row. When the address signals ADDy0 and ADDy1 are low, the RM signal is high, thereby blowing the fuse 331. This allows for the programming of the buffers 321 through 323. When the address signals ADD1 through ADD9 are high, all the buffers, i.e. the buffers 321M through 329M and the buffers 321N through 329N, are programmed so that their outputs are low. In the case of the buffer of FIG. 22, the transistor 380 should conduct so as to obtain a T1 signal from the address signal ADD1. As described above, in order to cause the transistor 380 to conduct, the fuse 371 should remain intact. That is, in the programming, the address signals ADD1 through ADD9 should-remain high so that the fuse 371 of the buffer will not be blown.

For each redundant row line which is to be used, a correct Y-address is supplied, so as to allow for programming of the buffer associated with that row line. Then, by using the correct address, the fuse 355 of FIG. 21 is blown. This prevents any additional programming.

FIG. 24 illustrates yet another fuse-blowing circuit which is different from the ones shown in FIGS. 20 through 23. The circuit of FIG. 24 is, for example, intended to replace the fuse 331 and the transistors 332 and 333 of FIG. 20, as in the fuse-blowing circuits shown in FIGS. 20 through 23. The fuse-blowing circuit of FIG. 24 includes a fuse 405, which may be the same as the polysilicon fuses described above. The fuse 405 is serially connected to a pair of transistors, i.e. an enhancement mode transistor 403 and a transistor 404, which are connected in parallel.

The transistor 404 has a threshold voltage of approximately 0V. Such a transistor is generally well-known and easily fabricated, for example, by adjusting the doping level of the channel of the transistor. The transistor 404 is relatively small as compared with the transistor 403. When a voltage of Vcc is applied to the gate of the transistor 403, the transistor 403 turns ON, and a strong current flowing on the transistor 403 blows the fuse 405. This current is similar to the current which flows through the transistor 229 of FIG. 20 and which blows the fuse 331. During normal operation, the transistor 404 receives Vcc at the gate, and, in the same manner as the transistor 332 of FIG. 20, keeps a node 402 at the ground potential when the fuse 405 is blown.

According to the fuse-blowing circuit of FIG. 23, the resistance of the fuse 405 can be checked to confirm that the fuse 405 has been blown. After the fuse 405 is blown, the fuse 405 is not always completely open at both ends. If the fuse 405 is not completely open, the remaining material can have a sufficiently low resistance to cause the problem that the node 402 is not brought to the ground potential.

Suppose that the fuse 405 is not completely blown, and that the fuse 405 has a resistance even after being blown. To check the resistance of the fuse 405, it is necessary to drop the fuse screen voltage Vfs supplied to the gate of the transistor 404. At this voltage, the transistor 404 slightly conducts, and the node 402 rises toward the voltage which is normally Vcc applied to the fuse for testing. Thus, by applying a relatively low voltage to the transistor 404 and the like transistors, and by detecting the potential on the node 402, the effectiveness of the step of blowing the fuse 405 can be checked.

In another embodiment, the transistor 404 may be replaced by a depletion mode transistor. During normal operation, the gate of the transistor 404 is fixed at the ground potential. To check the resistance of the fuse 405 which has been blown, the gate is brought to a negative potential at which the depletion mode transistor conducts only slightly.

In the foregoing embodiments, a fuse is used for programming the decoders and the other circuits which require programming.

FIG. 25 illustrates a circuit which is intended to replace a fuse and a fuse-blowing circuit of FIGS. 20 through 23. When the circuits of FIGS. 22 and 25 are compared, transistors 406, 407, and 408 of FIG. 25 correspond to the transistors 368, 369, and 370 of FIG. 22. The circuit on the side of the transistor 410 replaces the fuse 371 and the transistors 372 and 373 of FIG. 22. The signal on the signal line 374 is equivalent to the signal on a signal line 415 except that the signal on the signal line 415 is a complement of the signal on the signal line 374.

The circuit on the side of the transistor 410 of FIG. 25 includes a memory element 411. Usually, such an element is serially connected to an element such as the transistor 413. A preferred embodiment for the nonvolatile memory elements of Embodiments 1 through 8 is described in U.S. Pat. No. 4,203,158. A transistor 412 is connected in parallel with the memory element 411. A transistor 413 is connected to Vcc through a depletion mode transistor 414. The circuit of FIG. 25 operates in the same manner as the circuits of FIGS. 22 and 23, except that, rather than blowing a fuse, charge is transmitted to the memory functioning member of the memory element 411.

Thus, in a redundancy circuit for a single chip memory, no additional pins are required for programming the redundancy circuit, and such programming is carried out once the memory chip has been packaged. Once the programming has been completed, the programming circuit is disabled, thereby preventing inadvertent programming.

As described above, a redundancy circuit of the present invention is provided in a semiconductor storage device including a plurality of memory elements, each of which includes (i) a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, (ii) a channel region provided under the gate electrode, (iii) diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and (iv) memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge. The redundancy circuit includes programmable decoder means for selecting a redundant row line when the memory receives a predetermined row address signal corresponding to a defective row line, and selecting section which receives address signals of second lines (bit lines). The selecting section includes an arrangement for selecting the programmable decoder means during write/erase operation so as to prevent further programming. Once the defective line is thus replaced by the redundant line in the memory array, any additional programming is permanently prevented. When the redundant line is selected, all unassociated lines are deselected.

The memory element has the following effects when used instead of conventional flash memories.

In each memory element, the memory function and the transistor function are separated; the memory function is performed by the memory functioning member, and the transistor function is performed by the gate insulating film. Therefore, it is possible to reduce the thickness of the gate insulating film while preserving a sufficient memory effect, thereby attaining miniaturization while preventing the short-channel effect.

Because the memory element is easy to miniaturize, the increase of the chip area is modest as compared with conventional art even if the redundancy circuit of the present invention is provided.

The memory functioning member of each memory element includes a film whose surface is substantially parallel to a surface of the gate insulating film, the film having a function of holding charge. This prevents variation of the memory effect and, during memory-holding, change of characteristics. The yield of the chips is thus improved, thereby reducing costs. In addition, because the number of redundancy circuits provided in preparation for defects can be reduced, it is possible to suppress the increase of the chip size does not increase.

The fabrication process of the memory element has high conformity to the fabrication process of an ordinary transistor. Therefore, the number of masks and the number of processing steps can be drastically reduced as compared with a case where a conventional flash memory is used as a nonvolatile memory element in combination with a peripheral circuit including ordinary transistors. This improves the yield of the chips, thereby reducing costs, and allows for the reduction of the number of redundancy circuits, thereby suppressing the increase of the chip area.

[Embodiment 11]

One of application examples of the semiconductor storage device is a non-volatile memory as shown in FIG. 27. The non-volatile memory, which is rewritable, is used for adjusting an image in a liquid crystal panel.

A liquid crystal panel 1001 is driven by a liquid crystal driver 1002. The liquid crystal driver is provided with a non-volatile memory section 1003, an SRAM section 1004, and a liquid crystal driver circuit 1005. The non-volatile memory section 1003 is provided with a memory element of any of Embodiments 1 through 8. It is more preferable that the memory element provided in the non-volatile memory section 1003 is the semiconductor storage device described in Embodiment 10. The non-volatile memory section 1003 can be rewritten by external operation.

Data stored in the non-volatile memory section 1003 is transferred to the SRAM section when the liquid crystal panel 1001 is powered on. The liquid crystal driver circuit 1005 can read out the stored data from the SRAM section when necessary. With the arrangement in which the SRAM section is provided, it is possible to attain a very fast read-out of the stored data.

The liquid crystal driver 1002 may be, as shown in FIG. 26, provided externally of the liquid crystal panel 1001, but may be formed on the liquid panel 1001.

In liquid crystal panels, a gray level to be displayed is changed by applying multi-leveled voltages on each pixel. However, different liquid crystal panels have different relationships between the applied voltage and the gray level to be displayed. Therefore, with an arrangement in which date for compensating unevenness among individual liquid crystal panels is stored in the liquid crystal panels after being produced, it is possible to attain even image quality among the liquid crystal panels by performing compensation based on the data. Therefore, it is preferable that the liquid crystal panel is provided with a rewritable non-volatile memory for storing the data for the compensation. It is preferable to use the memory element of the present embodiment as the non-volatile memory. Especially, it is preferable to use the semiconductor storage device described in Embodiment 10. In the semiconductor storage device described in Embodiment 10, the memory elements of the present embodiment are integrated.

By using the memory element of the present embodiment as the non-volatile memory for adjusting the image in the liquid crystal panel, it is possible to attain low manufacturing cost because it is easy to mount the memory element of the present embodiment, on one chip, together with a circuit such as a liquid crystal driver and the like. Moreover, the semiconductor storage device described in Embodiment 10 is especially suitable for usage in which a relatively small memory capacity is required while high reliability and stability are necessary. In general, the non-volatile memory for adjusting the image in the liquid crystal panel is, for example, several kilo bites and thus has a relatively small memory capacity. Therefore, it is especially preferable to use the semiconductor storage device described in Embodiment 10 as the non-volatile memory for adjusting the image in the liquid crystal panel.

[Embodiment 12]

FIG. 30 shows a portable telephone, which is a portable electronic apparatus including the semiconductor storage device described in Embodiment 10.

The portable telephone is mainly provided with a control circuit 811, an electric battery 812, an RF (Radio Frequency) circuit 813, a display section 814, an antenna 815, a signal line 816, a power line 817, and the like. The control circuit 811 is provided with the semiconductor storage device described in Embodiment 10. It is preferable that the control circuit 811 is an integrated circuit which has the arrangement as described in Embodiment 10, and which functions as both a memory circuit element and a logic circuit element. With this arrangement, it becomes easier to produce the integrated circuit and reduce a production cost of the portable electronic apparatus, especially.

As described above, it is possible to attain faster operation speed and lower production cost of the portable electronic apparatus by using the semiconductor storage device in the portable electronic apparatus, the semiconductor storage device being advantageous in allowing easy process of mounting together a logic circuit section and a memory section and in attaining a high-speed read-out. Therefore, it is possible to attain a portable electronic apparatus having a low cost, a high reliability and high performance.

The invention being thus described, it will be obvious that the same way may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims. 

1. A redundancy circuit provided in a semiconductor storage device including a plurality of memory elements, first lines selected by first address signals, and second lines selected by second address signals, wherein: each of the memory elements includes a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge, the redundancy circuit comprising a plurality of redundant lines, programmable decoder means for selecting the redundant lines upon receipt of predetermined ones of the first address signals, the decoder means being programmed so as to recognize said predetermined ones of the first address signals, and selecting means which receives at least a part of the second address signals, the second address signals being for selecting the programmable decoder means during programming and for disabling programming of the programmable decoder means upon receipt of a certain signal.
 2. The redundancy circuit as set forth in claim 1, wherein: the programmable decoder means includes a fuse, and two transistors serially connected to the fuse and connected to each other in parallel, one of the two transistors having a threshold voltage of substantially zero volts; and the programming being performed by blowing the fuse through the transistors.
 3. The redundancy circuit as set forth in claim 1, wherein: the programmable decoder means includes a memory cell which is electrically erasable and electrically programmable, the programmable decoder means being programmed by the memory cell.
 4. The redundancy circuit as set forth in claim 1, wherein: the selecting means include a disabling fuse; and the programming of the programmable decoder means is disabled by blowing the disabling fuse upon the receipt of the certain signal.
 5. The redundancy circuit as set forth in claim 2, wherein: the selecting means include a disabling fuse; and the programming of the programmable decoder means is disabled by blowing the disabling fuse upon the receipt of the certain signal.
 6. The redundancy circuit as set forth in claim 3, wherein: the selecting means include a disabling fuse; and the programming of the programmable decoder means is disabled by blowing the disabling fuse upon the receipt of the certain signal.
 7. The redundancy circuit as set forth in claim 3, wherein: the certain signal is a predetermined second address.
 8. The redundancy circuit as set forth in claim 2, wherein: the fuse is a polysilicon fuse which is selectively blown.
 9. The redundancy circuit as set forth in claim 4, wherein: the disabling fuse is a polysilicon fuse which is selectively blown.
 10. The redundancy circuit as set forth in claim 5, wherein: the disabling fuse is a polysilicon fuse which is selectively blown.
 11. The redundancy circuit as set forth in claim 6, wherein: the disabling fuse is a polysilicon fuse which is selectively blown.
 12. The redundancy circuit as set forth in claim 2, wherein: the programmable decoder means blows or leaves intact the fuse so as to select a true one of the first address signals or a complement of said one of the first address signals.
 13. A redundancy circuit as set forth in claim 1, further comprising: deselecting means for deselecting a defective one of the redundant lines.
 14. A redundancy circuit as set forth in claim 2, further comprising: deselecting means for deselecting a defective one of the redundant lines.
 15. A redundancy circuit as set forth in claim 3, further comprising: deselecting means for deselecting a defective one of the redundant lines.
 16. A redundancy circuit provided in a semiconductor storage device including a plurality of memory elements, first lines selected by first address signals, second lines selected by second address signals, a plurality of array decoders which receive the first address signals, and a plurality of array lines selected by the array decoders, wherein: each of the plurality of memory elements includes a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge, the redundancy circuit comprising a plurality of redundant lines, a plurality of redundant decoders for selecting the redundant lines, the redundant decoders being connected to the array decoders so as to prevent selection of the array lines upon selection of one of the redundant lines, programmable gate means which receives the first address signals, the programmable gate means being programmed so as to supply predetermined ones of the first address signals to the redundant decoders, selecting means which receives the second address signals, the second address signals being for selecting the programmable gate means during programming of the programmable gate means, and preventing means for preventing the programming of the programmable gate means, the preventing means being activated by predetermined ones of the second address signals.
 17. The redundancy circuit as set forth in claim 16, wherein: the programmable gate means includes a fuse, and two transistors serially connected to the fuse and connected to each other in parallel, one of the two transistors having a threshold voltage of substantially zero volts; and the programming being performed by blowing the fuse through the transistors.
 18. The redundancy circuit as set forth in claim 16, wherein: the programmable gate means includes a polysilicon fuse which is selectively blown.
 19. The redundancy circuit as set forth in claim 18, wherein: blowing of the polysilicon fuse controls selection of true and complement ones of the first address signals.
 20. The redundancy circuit as set forth in claim 16, wherein: the preventing means includes a polysilicon fuse which is blown so as to prevent the programming.
 21. A redundancy circuit as set forth in claim 16, further comprising: deselecting means for deselecting a defective one of the redundant lines.
 22. A semiconductor storage device, comprising: a plurality of memory elements including a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge; first lines selected by first address signals; second lines selected by the second address signals; and the redundancy circuit as set forth in claim 1, the memory functioning member of the memory element including a film whose surface is substantially parallel to a surface of the gate insulating film, the film having a function of holding charge.
 23. A portable electronic device including the semiconductor device as set forth in claim
 22. 24. A semiconductor storage device, comprising: a plurality of memory elements including a gate electrode provided on a semiconductor layer, a gate insulating film intervening between the gate electrode and the semiconductor layer, a channel region provided under the gate electrode, diffusion regions respectively provided at both sides of the channel region, the diffusion regions having a conductivity type which is opposite a conductivity type of the channel region, and memory functioning members respectively provided at both sides of the gate electrode, the memory functioning members having a function of holding charge; first lines selected by first address signals; second lines selected by the second address signals; and the redundancy circuit as set forth in claim 16, the memory functioning member of the memory element including a film whose surface is substantially parallel to a surface of the gate insulating film, the film having a function of holding charge.
 25. A portable electronic device including the semiconductor device as set forth in claim
 24. 26. A redundancy circuit provided in a semiconductor storage device including a plurality of memory elements, a first line selected by a first set of address signals, and a second line selected by a second set of address signals, wherein: each of the memory elements includes a semiconductor layer including a channel region having a first conductivity type, a gate insulating film disposed on the semiconductor layer over the channel region, and a gate electrode disposed on the gate insulating film, first and diffusion regions on opposite sides of the channel region having a second conductivity type opposite the first conductivity type, and charge holding memory functioning members provided at opposite sides of the gate electrode, the redundancy circuit comprising: a first redundant line and a second redundant line, a first programmable decoder circuit for selecting the first redundant line upon receipt of the first set of address signals, the first programmable decoder circuit being placed into a programmable state by a programming signal on a programming line, and a selecting circuit carrying the programming signal, the selecting circuit including a disabling circuit for disabling the selecting circuit, and the programming of the first programmable decoder, upon receipt of a signal. 